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PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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Clarivate Analytics published the InCites Journal Citations Report for 2022. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.800 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 1.000.

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  1/2022 - 5

Reduction in Total Harmonic Distortion in Induction Motor Drives with High-Performance FPGA Controller

SUMAM, M. J. See more information about SUMAM, M. J. on SCOPUS See more information about SUMAM, M. J. on IEEExplore See more information about SUMAM, M. J. on Web of Science, SHINY, G. See more information about SHINY, G. on SCOPUS See more information about SHINY, G. on SCOPUS See more information about SHINY, G. on Web of Science
 
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Download PDF pdficon (3,688 KB) | Citation | Downloads: 700 | Views: 1,117

Author keywords
field programmable gate arrays, induction motor, pulse width modulation inverters, space vector pulse width modulation, total harmonic distortion

References keywords
electronics(22), industrial(15), power(14), applications(12), multilevel(11), voltage(8), space(8), control(8), inverters(7), converters(7)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2022-02-28
Volume 22, Issue 1, Year 2022, On page(s): 39 - 46
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2022.01005
Web of Science Accession Number: 000762769600005
SCOPUS ID: 85126823628

Abstract
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This paper proposes the design and development of a space vector pulse width modulated v/f controller in FPGA for a three-phase multilevel inverter. The complexity of the modulation scheme and the switching signal generation for motor drives rises with the increase in the number of levels of the inverter. Due to the sequential processing of instructions, microprocessors and digital signal processors are unable to execute short duration pulse width modulated switching signals in real-time, resulting in harmonic distortion. The proposed algorithm is implemented in FPGA to get a dynamic response and to improve the harmonic performance. All of the controller's modules are embedded in a single FPGA and operate in synchronism with a single clock. The controller is validated with a 4-Level inverter, which drives an open-end winding induction motor. Because of algorithm optimization, single clock synchronization, and FPGA parallel processing, the controller has less than 1% total harmonic distortion. There is no need for bulky and costly harmonic reduction filters with this design technique. The proposed scheme shows much better harmonic performance compared to other higher-level schemes.


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Faculty of Electrical Engineering and Computer Science
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