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FACTS & FIGURES

JCR Impact Factor: 0.825
JCR 5-Year IF: 0.752
SCOPUS CiteScore: 2.5
Issues per year: 4
Current issue: Feb 2023
Next issue: May 2023
Avg review time: 76 days
Avg accept to publ: 48 days
APC: 300 EUR


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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FEATURED ARTICLES

A Wind Energy Prediction Scheme Combining Cauchy Variation and Reverse Learning Strategy, WU, X., SHEN, X., ZHANG, J., ZHANG, Y.
Issue 4/2021

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LATEST NEWS

2022-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2021. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.825 (0.722 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.752.

2022-Jun-16
SCOPUS published the CiteScore for 2021, computed by using an improved methodology, counting the citations received in 2018-2021 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering in 2021 is 2.5, the same as for 2020 but better than all our previous results.

2021-Jun-30
Clarivate Analytics published the InCites Journal Citations Report for 2020. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.221 (1.053 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.961.

2021-Jun-06
SCOPUS published the CiteScore for 2020, computed by using an improved methodology, counting the citations received in 2017-2020 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering in 2020 is 2.5, better than all our previous results.

2021-Apr-15
Release of the v3 version of AECE Journal website. We moved to a new server and implemented the latest cryptographic protocols to assure better compatibility with the most recent browsers. Our website accepts now only TLS 1.2 and TLS 1.3 secure connections.

Read More »


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Year: 2015, Volume: 15, Number: 3
... package with the 2014. [Online]. Available: http://dx.doi.org/10.1007/s10844-014- implementation of the approach. It is available to download 0319-2 [17] U. Markowska-Kaczmar and A. Hurej, "Evaluation of subspace at http://marosz.kia.prz.edu.pl/subspace.html. clustering quality," ...
Terms matched: 1  -  Score: 3  -  1,251k
Year: 2016, Volume: 16, Number: 1
... urban driving cycle and is intended to 396 48 1000 60.1268 represent city driving conditions. It is characterized by low 396 38.4 800 59.0657 vehicle speed and low engine load. The Extra Urban Driving 396 41.6 900 58.3103 Cycle (EUDC) has been designed to represent more 396 48 1100 55.942 396 38.4 900 54.7941 aggressive driving ...
Terms matched: 1  -  Score: 3  -  1,239k
Year: 2018, Volume: 18, Number: 3
... using the powerful image editing tools are increasing day-by-day. As a result, near The existence of these near duplicate images in the web duplicate images are created and uploaded on the Web. ND image search indicates the presence of redundancy and images are the minor variants of the original image which is represents violations of copyright. ...
Terms matched: 1  -  Score: 3  -  1,424k
Year: 2010, Volume: 10, Issue: 1
... by the lead speed of the strip, v1. The signal respect to the minimization of the error variance, h. In the given by the transducer is loaded in a shift register that case of the rolling process with several passes, each pass is exists into the controller (LI in Fig. 3). ...
Terms matched: 1  -  Score: 3  -  508k
Year: 2018, Volume: 18, Number: 3
... for manner and therefore, when compared to ASIC and FPGA- customization, users can implement digital circuit designs based applications, a good speed performance cannot be by uploading the configuration file. Since the configuration obtained from DSP chips in ANN applications. Although of these chips takes very little time, circuit designs can be quite ...
Terms matched: 1  -  Score: 3  -  1,552k
Year: 2013, Volume: 13, Number: 3
... the max-max 20.30% 16.87% proper value of , the performance of the proposed Curve fitting 10.78% approach is quite promising after comparing with other The computational loading for curve fitting method grey-fuzzy methods, the curve fitting method, and the neural involves inverses of a matrix, while for the grey-fuzzy network method. The ...
Terms matched: 1  -  Score: 3  -  720k
Year: 2013, Volume: 13, Number: 3
... www.alphaworks.ibm.com/tech/cellsw?open&S_TA [6] A. Navarro, R. Asenjo, S. Tabik, and C. Cascaval. "Load Balancing CT=105AGX16&S_CMP=DWPA. using Work-Stealing for Pipeline Parallelism in Emerging [19] K. Y. Hsieh, C. H. Lai, ...
Terms matched: 1  -  Score: 3  -  888k
Year: 2013, Volume: 13, Number: 4
... " [5 ], this FOP consists of four identical modules in its structure- a, b, c, d. All external bus are intended to load from the memory a component of the quaternion and send the results to memory operations. Each module (Figure 3) contains a matrix multiplier MPM1 and MX2 ...
Terms matched: 1  -  Score: 3  -  777k
Year: 2018, Volume: 18, Number: 2
... Kim. "Prediction of doi:10.1016/j.engappai.2014.09.008 persistent hemodynamic depression after carotid angioplasty and [26] A. Glowacz. "Recognition of Acoustic Signals of Loaded stenting artificial neural network model," Clinical Neurology and Synchronous Motor Using FFT, MSAF-5 and LSVM," Archives of Neurosurgery, vol. 164, pp ...
Terms matched: 1  -  Score: 3  -  1,031k
Year: 2013, Volume: 13, Number: 4
... stage, the using vTclk cycles. At the same time, the content of the R2 addition within S1 stage, two stages corresponding to the S2 register is loaded in parallel with the updated check nodes additions, ROM memory data read within S3 stage, the values (R3), and the R1 content is also ...
Terms matched: 1  -  Score: 3  -  609k
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